Global Instruction Scheduling In Machine SUIF

The Flow Analysis and Transformation

Machine SUIF 6] is an extension of the SUIF compiler framework that facilitates experiments with machine-speciic optimizations. Just as base SUIF 7] is built on a rich collection of libraries for machine-independent analysis and transformation, machine SUIF has a growing set of libraries for working at the machine level. This note is about the libraries for ow analysis to support ow-directed tr...

Using SUIF as a Front-end Translator for Register Allocation and Instruction Scheduling Research

Developing a back-end for the ARM v5 architecture within the machine SUIF infrastructure

Future processor design requires complex techniques and tools to acquire good performance without compromising power-aware. So there is an urgent need of tools which allow to study the main processor characteristics in an easy way and, with a good level of detail before manufacturing the chip. Simulators and experimental compilers are the unique tools ready to reach these ambitious objectives. ...

Compiler Optimization for Superscalar Systems: Global Instruction Scheduling without Copies

Vol. 10 No. 1 1998 Many of today’s computer applications require computation power not easily achieved by computer architectures that provide little or no parallelism. A promising alternative is the parallel architecture, more specifically, the instruction-level parallel (ILP) architecture, which increases computation during each machine cycle. ILP computers allow parallel computation of the lo...

Efficient code generation for ASIPs with different word sizes

We propose a complete methodology for extending our automatic ASIP (Architecture Specific Instruction set Processor) synthesis framework to a much wider target architecture space. In this new architecture space the width of the integer data word and of any hardware resource data path is user-definable and application specific. This methodology, developed on the basis of a retargetable C compile...